In a semiconductor device of a trench gate type, when excessive concentration of an electric field occurs at a bottom of an insulated gate, the semiconductor device may be broken. For the purpose of preventing the electric field concentration, for example, Japanese Patent Application Publication No. 2009-88360 (Patent Document 1) has disclosed a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) in which an insulated gate of a trench type is formed in a cell region, and a trench filled with an insulator is formed in a peripheral region that is a non-cell region. The trench filled with the insulator is formed in a p-type resurf layer in the peripheral region. When a voltage is applied across source and drain electrodes of the MOSFET, a depletion layer spreading from a pn junction of the MOSFET expands until it reaches the trench filled with the insulator in the peripheral region. This uniformizes the spreading of the depletion layer in the peripheral region, and improves a breakdown voltage of the MOSFET.